1. Field
Example embodiments relate generally to a latency signal generator and method thereof.
2. Description of the Related Art
A conventional synchronization semiconductor memory device may receive and transmit data in synchronization with an external clock signal. The synchronization semiconductor memory device may set, in advance, the number of clock cycles in which valid data is output in response to a read command of a memory controller. The number of clock cycles between when a read command (or a column address) is input into the synchronization semiconductor memory device until corresponding data (e.g., read response data) is output to an external entity may be referred to as “CAS latency”. A latency signal generator included in the synchronization semiconductor memory device may control data so as to conform to the CAS latency.
FIG. 1 is a block diagram illustrating a conventional synchronization semiconductor memory device including a latency signal generator.
Referring to FIG. 1, the synchronization semiconductor memory device may include a mode register 101 for outputting CAS latency CLi set by a mode register set command MRS CMD, a read command buffer 102 for generating an internal read command PREAD from a read command READ CMD, an internal clock generator 103 for receiving an external clock signal EXCLR and generating an internal clock signal PCLK, a clock synchronization circuit 104 for generating a data output clock signal CLKDQ based on the external clock signal EXCLK, a latency signal generator 110 for generating a latency signal S_LATENCY, an address buffer 133 for receiving an address ADDRESS and outputting a row address signal Add_R and a column address signal Add_C, a row decoder 131, a column decoder 132, a memory cell array 130 for outputting memory cell data DATA and a data output buffer 120. Referring to FIG. 1, the clock synchronization circuit 104 may be a delay locked loop (DLL).
Referring to FIG. 1, the latency signal generator 110 may receive the CAS latency CLi, the internal read command PREAD, the internal clock signal PCLK, and the data output clock signal CLKDQ, and may generate a latency signal S_LATENCY. The data output buffer 120 may output output data DOUT to an external entity based on the data output clock signal CLKDQ if the latency signal S_LATENCY is output.
FIG. 2 is a circuit diagram illustrating the latency signal generator 110 of FIG. 1. Referring to FIG. 2, the latency signal generator 110 may support 12 CAS latency modes.
Referring to FIG. 2, a plurality of flip-flops F101 through F112 may generate a plurality of sequential sampling clock signals SCLK01 through SCLK12 in response to an internal clock signal PCLK. A plurality of multiplexers MUX01 through MUX12 may respectively adjust the sequence of the plurality of sequential sampling clock signals SCLK01 through SCLK12 corresponding to the CAS latency CLi so as to output a plurality of sampling clock signals SCLKD01 through SCLKD12, respectively. A plurality of flip-flops F201 through F212 may latch an internal read command PREAD based on the plurality of sampling clock signals SCLKD01 through SCLKD12, respectively.
Referring to FIG. 2, a plurality of flip-flops F301 through F312 may generate a plurality of transfer control signals TCLK01 through TCLK12, respectively, according to a data output clock signal CLKDQ. A plurality of switches SW01 through SW12 may control the output of the plurality of flip-flops F201 through F212, respectively, in response to the plurality of transfer control signals TCLK01 through TCLK12, respectively. An output latch L_out may receive the outputs FS01 through FS12 of the plurality of flip-flops F201 through F212, respectively, which may be controlled by the plurality of switches SW01 through SW12, respectively, and may output a latency signal S_LATENCY.
Conventional operation of the latency signal generator 110 illustrated in FIG. 2 is well-known in the art and will not be described further for the sake of brevity.
Generally, as an operating speed of a conventional synchronization semiconductor memory device increases, it may become more difficult for the conventional synchronization semiconductor memory device to accommodate multiple CAS latency modes. Accordingly, the latency signal generator 110 may be configured to generate a plurality of latency signals corresponding to a given CAS latency having a given number of clock cycles.
However, in order to generate a latency signal corresponding to CAS latency having a higher value using the latency signal generator 110 having the structure as illustrated in FIG. 2, the number of flip-flops and multiplexers may scale with the number of clock cycles (e.g., the amount of delay), which may increase the circuit area of the latency signal generator 110, and may likewise increase a logic delay during latency signal generation.